1. Field of the Invention
The invention relates to semiconductor devices and more particularly to reduced feature size devices and the fabrication of the same.
2. Description of Related Art
A major goal of metal oxide semiconductor field effect transistor (MOSFET) scaling is to increase the density and speed of the integrated circuits in which such scaled-down devices are utilized. Devices are formed on a semiconductor substrate typically by depositing material and then patterning that material to remove specific portions on the wafer surface. Optical lithography has been used to pattern and generate device structures down to 0.2 micron (xcexcm) geometry. As the minimum feature size continues to be scaled down to sub-0.10 xcexcm, other techniques, such as electron-beam (E-beam) lithography, x-ray lithography, or extreme ultraviolet (EUV) lithography have been attempted. These latter lithography methods are generally expensive and have presented many technical barriers to widespread use.
As technologies shrink, it is increasingly difficult to obtain performance increases. Increasing device density typically means using devices with smaller channel lengths and widths. Increasing the speed of integrated circuits is generally accomplished by increasing the saturation drain current (IDsat). Increasing the MOSFET IDsat allows faster charging and discharging of parasitic capacitances. IDsat is increased typically by either a decrease in the channel length or a decrease in the gate oxide thickness.
One factor that has not proved possible to scale is the transistor mobility. The electron and hole mobilities are a measure of the ease of carrier motion in a semiconductor crystal. In the semiconductor bulk, the carrier mobilities are typically determined by the amount of lattice scattering and ionized impurity scattering taking place inside the material. Carrier transport in the MOSFET, however, primarily occurs in the surface inversion layer. In small feature size devices, the mobility due to the gate-induced electric field (i.e., transverse electric field) and drain-induced electric field (i.e., longitudinal electric field) act on the carriers and significantly influence the velocity of the moving carriers in the inversion layer of a device channel. The drain-induced electric field acts to accelerate the carriers parallel to the Sixe2x80x94SiO2 interface, whereupon the carrier suffers scattering similar to as in the bulk. The gate-induced electric field, however, also causes the carriers to be accelerated toward the Sixe2x80x94SiO2 surface. Thus, the carriers near the surface experience additional motion-impeding collisions with the silicon surface. As a result, the carrier mobility at the surface is observed to be lower than in the bulk. These and other scattering mechanisms cause the mobility to saturate at what is termed velocity saturation. Velocity saturation prevents increases in mobility expected from decreases in gate length.
It has been shown theoretically that it is possible to greatly enhance the mobility of a silicon MOS transistor by an order of magnitude if the width of the device is of the order of 100 angstroms (xc3x85). This conclusion rises from the fact that the width of the transistor (i.e., the channel) is of a dimension such that it forms a potential box, that causes thin strips of the channel to become quantized in the width direction, similar to the quantization of the inversion layer in the MOS transistor in the xe2x80x9cZxe2x80x9d direction (at the gate oxide interface). With strips of channel of approximating 100 xc3x85 width, the inversion layer becomes quantized in the width direction resulting in an inversion layer for these very thin transistors that resembles a series of quantum wires, with the density of electrons limited to the middle of the channel. Consequently, these transistors do not suffer the two-dimensional scattering that MOSFET devices normally undergo. The consequences of this are that it is possible to obtain transistors whose mobilities are theoretically increased by at least an order of magnitude over conventional devices. However, forming transistors on the order of 100 xc3x85 and quantizing the transistors"" channels has to date been difficult to achieve with existing formation techniques.
A method of forming reduced feature size spacers is disclosed. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having a first thickness and opposing side portions; patterning a pair of second spacers, each second spacer adjacent to a side portion of the first spacer, each second spacer having a second thickness in opposing side portions, wherein the second thickness is less than the first thickness; removing the first spacer; patterning a plurality of third spacers, each third spacer adjacent to one of the side portions of one of the second spacers, each one of the third spacers having a third thickness, wherein the third thickness is less than the second thickness; and removing the second spacers. A semiconductor apparatus formed by this method is also disclosed.
A field of effect transistor is further disclosed. The transistor includes a semiconductor substrate having a source region and a drain region; a gate area of the substrate surface; a channel region in the substrate having a cross-sectional area defined by a portion of the gate area, a channel length measured across a portion of the channel region between the source region and the drain region; and a trench formed in a portion of the channel region, the trench having a trench length substantially equivalent to the channel length.
Additional features and benefits of the invention will become apparent from the detailed description, figures, and claims set forth below.